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HV583
HV583 128-Channel Serial to Parallel Converter with Push-Pull Outputs
Features
Processed with HVCMOS technology 128 Channels 4 Separate shift registers 5V CMOS logic Output voltages up to 80V 30mA output current capability Low power level shifting 40MHz data shifting Latched data outputs Forward and reverse shifting option via DIR pin Output diode to ground and VPP for efficient power recovery Outputs can be hot switched
General Description
The Supertex HV583 is a 128-channel low voltage serial to high voltage parallel converter with push-pull outputs. This device has been designed for use as a display driver. It can also be used in any application requiring multiple output, high voltage current sourcing and sinking capability such as plasma displays and inkjet printers. The device has 4 parallel 32-bit shift registers, permitting data rates 4X the speed of one. The data are shifted in during the low to high clock transition. There are also 128 latches and control logic to shift clockwise or counterclockwise. High at RST input pin clears contents of both: the shift register and the latch. The outputs can be in a high impedance state via the output enable logic pin.
Applications
Plasma Displays Inkjet Printers
Typical Application
Low Voltage Power Supply High Voltage Power Supply
Supertex HV583
DXA CLK RST LE Micro Processor OE OL OH
DXB
HVOUT0
Columns
Low Voltage
High Voltage
Shift Register Latches Output Contr.
Level Translators & Push-Pull Output Buffers
Row Driver
HVOUT127
Display Panel
DXA for cascading the next HV583
Supertex HV583
1
HV583 Ordering Information
Device HV583 Recommended Operating VPP Max 80V Package Options Die HV583X
Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, etc.) to a known state. 4. Apply VPP.
-0.5V to +90V -0.5V to +7.0V -65mA to +40mA -65mA to +65mA -0.5V to VDD+0.5V -25C to +150C -40C to +150C
Absolute Maximum Ratings*
VPP, High voltage supply VDD, Logic supply voltage IOUT, Output source and sink current IDIODE, Output body diode current Logic input voltages Tj, Junction temperature Storage temperature
Power-down sequence should be the reverse of the above.
*All voltages are referenced to device ground. Absolute maximum ratings are those values which damage to the device may occur. Functional operation under these conditions is not implied. Continous operation of the device at the absolute rating level may affect device reliability.
Operating Conditions
Symbol VPP VDD IOUT SR fCLK Tj Parameter High voltage supply Low voltage supply HVout peak output current VPP power supply slew rate Clock frequency Min 15 4.5 -30 5.0 Typ Max 80 5.5 30 8.0 40 25 Operating junction temperature -25 +125 Units V V mA V/s MHz MHz C Data read Cascade connection Conditions Cload = 300pF
Electrical Characteristics
DC Characteristics (Tj = 25C, VDD = 5V, VPP = 80V)
Symbol IPPQ IDDQ HVOH HVOHD HVOL HVOLD VIH VIL IIH IIL VOH VOL Parameter VPP quiescent supply current VDD quiescent supply current High level output voltage 73 10 Output p-channel body diode Low level output voltage Output n-channel body diode Logic input high voltage Logic input low voltage Logic input high current 10 Logic input low current Logic output high Logic output low 2 -1.0 4.5V 0.5V 30 -1.5 2.0 0 VDD 0.8 1.0 50 3.0 81.5 6.0 76 V V V V V V A A A V V Min Typ Max 10 10 Units A A IOUT = 30mA, VPP = 80V IOUT = 10mA, VPP = 20V IOUT = -30mA, VPP =80V IOUT = -30mA IOUT = +30mA VDD = 4.5V to 5.5V VDD = 4.5V to 5.5V VIH = 5.3V, VDD = 5.0V VIH = 5.0V, For DIR only VIL = -0.3V IOUT = 1.0mA IOUT = -1.0mA Conditions
HV583 AC Electrical Characteristics (Tj = 25C, VDD = 5V, VPP = 80V)
Symbol twCLK twLE tsu1 tsu2 tsu3 th1 th2 tpdHL tpdLH tpHL tpLH tpHZL tpLZH tpHZ tpLZ tr tf Parameter Clock pulse width, high and low LE pulse width, high and low Setup time, DXAs, DXBs to CLK Setup time, CLK to LE Setup time, LE to OL, OH Hold time, CLK to DXAs, DXBs Hold time, LE to CLK CLK to DXAs, DXBs CLK to DXAs, DXBs LE, OH, OL to HVOUT LE, OH, OL to HVOUT OE to HVOUT OE to HVOUT OE to HVOUT OE to HVOUT HVOUT HVOUT Min 10 10 5 10 25 5 10 25 25 150 Typ -20 tpHL+tf Typ +40 150 Typ -20 tpHL+tf Typ +40 300 300 120 120 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns C=15pF C=15pF C=50pF C=80pF C=50pF C=80pF Rl=10K, C=50pF Rl=10K, C=50pF C=50pF C=50pF Conditions VDD =4.5V to 5.5V, T25C to 125C VDD =4.5V to 5.5V, Tj=-25C to 125C
Shift Register Truth Table
DIR L or open L or open H H CLK L to H H to L L to H H to L State of Shift Register Shift Hold Shift Hold Shift Direction DXB to DXA DXB to DXA DXA to DXB DXA to DXB
Latch Truth Table
LE L to H H to L Output State of Latch Latch execution Hold
HVOUT Truth Table
OE L H H H H OL X L H H H OH X X L H H DXA/DXB X X X L H HVOUT Z L H L H
H = Level High L = Level Low X = Don't care. Can be High or Low Z = High impedance. Open circuit.
3
HV583 Block Diagram
VDD VPP
D1A
D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
HVOUT0
D1B D2A
D2B Latch D3A
D3B D4A
SR
SR
SR
SR
D124 D125 D126 D127
Q124 Q125 Q126 Q127
D4B CLK DIR RST LE OH OL OE
HVOUT127
DGND
PGND
4
HV583
Timing Diagram
CLK tsu1 DXA/B (input)
twCLK
twCLK
th1
tsu1
th1
tpLH DXA/B (output) tsu2 LE tsu3 OL, OH th2
tpHL
twLE
twLE
OE
OE
50%
50%
LE. OH, OL tpHZ tpLZ HVOUTn 90% 10% tpLZH tpHZL 90% 10% 10% tr tf tpLH 90% tpHL 90% 10%
LE, OH, OL
HVOUTn tpHL HVOUTn tf tpLH = tpHL + tf tr
5
HV583 Pad Description
VPP VDD D1A to D4A D1B to D4B Dir CLK RST LE OE OL OH DGND PGND HVOUT0 to HVOUT127 High voltage supply for outputs. Low voltage logic supply Right data input/output. Input when Dir = H, Output when Dir = L. Left data input/output. Input when Dir = L, Output when Dir = H. Dir = L or open, DXB to DXA shift. Dir = H, DXA to DXB shift. Clock input. Data shifted from low to high transition. Resets latches. Latch enable. Data latches during rising edge LE. Output enable. HVOUT high impedance control. Output low bar. All HVOUT = low when this pin is low. OH bar input. All HVOUT = high when this pin is low. Digital logic ground. HVOUT output ground. High voltage outputs.
Pad Location
PGND PGND PGND PGND VPP VPP VPP VPP VPP VPP
HVOUT64
HVOUT63
HVOUT127 VPP VPP
PGND PGND VDD
HVOUT0 VPP VPP PGND PGND DGND
OH
OE
DGND
RST
D1A
D2A
D3A
D4A
OL
VDD
DIR
D4B
D3B
D2B
6
CLK
D1B
LE
HV583 Pad Coordinates
Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name VDD PGND PGND VPP VPP HVOUT127 HVOUT126 HVOUT125 HVOUT124 HVOUT123 HVOUT122 HVOUT121 HVOUT120 HVOUT119 HVOUT118 HVOUT117 HVOUT116 HVOUT115 HVOUT114 HVOUT113 HVOUT112 HVOUT111 HVOUT110 HVOUT109 HVOUT108 HVOUT107 HVOUT106 HVOUT105 HVOUT104 HVOUT103 HVOUT102 HVOUT101 HVOUT100 HVOUT99 HVOUT98 HVOUT97 HVOUT96 HVOUT95 HVOUT94 HVOUT93 HVOUT92 HVOUT91 HVOUT90 HVOUT89 HVOUT88 HVOUT87 HVOUT86 HVOUT85 HVOUT84 HVOUT83 HVOUT82 HVOUT81 HVOUT80 HVOUT79 HVOUT78 HVOUT77 HVOUT76 HVOUT75 HVOUT74 HVOUT73 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y 0 150 260 410 520 670 780 890 1000 1110 1220 1330 1440 1550 1660 1770 1880 1990 2100 2210 2320 2430 2540 2650 2760 2870 2980 3090 3200 3310 3420 3530 3640 3750 3860 3970 4080 4190 4300 4410 4520 4630 4740 4850 4960 5070 5180 5290 5400 5510 5620 5730 5840 5950 6060 6170 6280 6390 6500 6610 Pad # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name HVOUT72 HVOUT71 HVOUT70 HVOUT69 HVOUT68 HVOUT67 HVOUT66 HVOUT65 HVOUT64 VPP VPP PGND PGND VPP VPP PGND PGND VPP VPP HVOUT63 HVOUT62 HVOUT61 HVOUT60 HVOUT59 HVOUT58 HVOUT57 HVOUT56 HVOUT55 HVOUT54 HVOUT53 HVOUT52 HVOUT51 HVOUT50 HVOUT49 HVOUT48 HVOUT47 HVOUT46 HVOUT45 HVOUT44 HVOUT43 HVOUT42 HVOUT41 HVOUT40 HVOUT39 HVOUT38 HVOUT37 HVOUT36 HVOUT35 HVOUT34 HVOUT33 HVOUT32 HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 X 0 0 0 0 0 0 0 0 0 263.1 373.1 607.1 717.1 977.1 1087.1 1347.1 1457.1 1691.1 1801.1 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 Y 6720 6830 6940 7050 7160 7270 7380 7490 7600 7963.5 7963.5 7802.5 7802.5 7963.5 7963.5 7802.5 7802.5 7963.5 7963.5 7600 7490 7380 7270 7160 7050 6940 6830 6720 6610 6500 6390 6280 6170 6060 5950 5840 5730 5620 5510 5400 5290 5180 5070 4960 4850 4740 4630 4520 4410 4300 4190 4080 3970 3860 3750 3640 3530 3420 3310 3200 Pad # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 Name HVOUT22 HVOUT21 HVOUT20 HVOUT19 HVOUT18 HVOUT17 HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 HVOUT10 HVOUT9 HVOUT8 HVOUT7 HVOUT6 HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 HVOUT0 VPP VPP PGND PGND DGND D1B D2B D3B D4B CLK LE RST DGND DIR VDD OE OH OL D4A D3A D2A D1A X 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 2064.2 1940.2 1825.5 1710.8 1596.1 1481.5 1366.8 1252.1 1142.1 1032.1 922.1 812.1 697.4 582.7 468 355.3 238.6 123.9 Y 3090 2980 2870 2760 2650 2540 2430 2320 2210 2100 1990 1880 1770 1660 1550 1440 1330 1220 1110 1000 890 780 670 520 410 260 150 0 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1 -210.1
B091906
7

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